Multi-layer ceramic (MLC) substrates, such as are used for chip carriers, comprise a number of discrete ceramic sheets laminated and sintered together. Each sheet has conductive lines printed on its surface with a conductive substance such as a metal, for example, copper paste. Holes punched through the ceramic sheet before sintering of the sheet (the unsintered sheet is known in the art as a "green" sheet) are filled with the conductive paste to provide conductive connections or "vias" between layers of the substrate. Thus, for example, a chip mounted on a completed MLC substrate is electrically connected to an underlying circuit board through the lines and vias of the MLC. Reliable connections in the MLC are critical to achieving the expected performance of the chip; the reliability of the connections is highly dependent upon the integrity of the line-to-via junctions.
Typically, the manufacture of such MLC substrates starts with a glass ceramic powder that is formed into a slurry and cast into a large sheet similar to how a sheet of paper is made. The large cast sheet is then dried and cut into smaller blanks. Via holes are punched into the blanks, and the lines are screen printed onto the blanks using masks and a conductive paste. Then, the layers of the MLC are stacked together and laminated in a press, cut to size, and sintered in an oven to create a homogenous ceramic substrate. One or more terminal plating steps may then be performed, including attaching one or more layers of thin film interconnects on top of the substrate, before joining the chip to the substrate.
Referring now to FIG. 1, there is shown a typical mask 10 known in the art and used to print the conductive lines on the green sheet blanks. Mask 10 comprises line patterns 12 and 13 each having a rectangular base section 14 with a width w.sub.l connected a to circular "cap" section 16 with a diameter d.sub.c. Circular cap section 16 is intended to be aligned with a hole punched in the blank, such that the paste flows down into the hole, creating a conductive via. Line pattern 12 has a "jogged" end 15 that is at an angle, typically 90.degree. or 135.degree., to rectangular base section 14.
Referring now to FIG. 2, there is shown a cross section of a line-to-via connection 20 on a green sheet blank 22 as manufactured using a mask of the prior art such as mask 10 shown in FIG. 1. One known problem, which may be encountered in the creation of such MLC substrates, is that the mask may be misaligned with blank 22 such that the hole punched in the blank for the via 27 is not perfectly centered underneath cap section 16 on mask 10 (shown in FIG. 1). In such case, line-to-via connection 20 between conductive line 24 and conductive via 27 may comprise a necked region 28 within the cap 29.
Cap diameter d.sub.c is typically greater than via diameter d.sub.v and greater than width w.sub.l. For example, line 24 may have a width (w.sub.l in FIG. 1) of about 0.071 mm (2.8 mils), via 27 may have a diameter d.sub.v of about 0.089 to about 0.1 mm (about 3.5 to about 4 mils), and cap 29 may have a diameter d.sub.c of about 0.114 to about 0.127 mm (about 4.5 to about 5 mils), whereas the alignment capabilities of the mask to the blank may only provide alignment of the cap to the via within an accuracy of about 0.05 mm (2 mils). Necked region 28 comprises an area having a thickness t.sub.2 that is less than the thickness t.sub.1 of the remainder of line 24. This thinner area is subject to concentrated thermal fatigue stresses during normal operation of the chip, and may be susceptible to cracking, causing a major reliability problem for the MLC package.
An object of the present invention is to provide a method to solve the cracking problem using line-to-via connection structures and mask pattern structures that minimize necking.